High Speed Analog I/O designer
$143,800 - $230,000 USD yearly
Originally posted 24 July 2026 by the employer.
About the role
This role involves designing and optimizing interface buffer chips for DDR/LP5/5X/6 and chiplets in FinFET process nodes.
What you'll do
- Work with the chip team to understand specifications and identify circuit architectures.
- Design, simulate, and optimize high-speed DDR circuits and chiplet I/Os.
- Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE, and slicers.
- Oversee physical layout to minimize parasitics and process variation.
- Conduct thorough simulations to validate design performance and reliability.
- Analyze customer silicon data for design enhancement.
What you'll need
- Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
- At least 10 years of experience in analog design, with a focus on high-speed RX and Analog-Front-End design.
- Experience with FinFET technologies.
- Expertise in high-speed DDR I/O interface, chip-chip interface design and optimization.
- Strong knowledge of analog receiver circuits such as CTLE, DFE, FEE.
- Sound knowledge of transmitter circuits such as FIR filter, slew rate control, voltage and current mode drivers.
- Knowledge of design for reliability (EM, IR, aging, self-heating) and layout effects.
- Familiarity with custom digital design (high-speed logic paths, Serializer, De-serializer).
- Proficiency with analog design tools (e.g., Cadence Virtuoso, Maestro, Spectre, HSPICE) and simulation techniques.
- Understanding of signal integrity, timing analysis, and power management.
- Familiarity with industry standards and protocols related to DDR I/O, chiplet I/O, and RX design.
Skills: high-speed DDR I/O, chiplet I/Os, transmitter and receiver circuits, FinFET, Cadence Virtuoso
This role has been open 67 days — below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 42 | 1385 · 108 employers |
| Median days open | 162 d | 76 d (+86 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: high-speed DDR I/O, chiplet I/Os, transmitter and receiver circuits, FinFET, Cadence Virtuoso
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.