HBM SoC Physical Design Engineer
$121,000 - $205,000 USD yearly
Originally posted 31 July 2026 by the employer.
About the role
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of HBM SoC logic and base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging, and manufacturing teams to deliver signoff collateral for tape-out.
What you'll do
- Own physical implementation for SoC blocks and top-level designs, including floor-planning, placement, CTS, routing, and physical optimization.
- Drive timing closure across multi-mode/multi-corner (MMMC) scenarios and partner with RTL, architecture, and STA teams to converge designs.
- Integrate complex IP including controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, and PHY-adjacent logic.
- Perform and coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff.
- Partner with DFT teams to ensure scan and MBIST requirements are physically realizable without compromising PPA or schedule.
- Support tape-out execution via checklists, ECO flows, signoff reviews, and post-silicon debug correlation.
What you'll need
- Experience in SoC physical design implementation from netlist to GDSII on complex designs.
- Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
- Solid understanding of STA fundamentals, clocking, SDC constraints, and closure techniques including buffering, path shaping, and useful skew.
- Experience with power intent and power delivery considerations, including UPF/CPF concepts, power grid planning, and power gating.
- Familiarity with physical verification concepts, including DRC, LVS, ERC, parasitic extraction, and signoff handoff quality.
Nice to have
- Experience with HBM or DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 3 years of experience in a related field.
- Understanding of Agentic AI or willingness to learn Agentic AI to develop efficient workflows.
Skills: floor-planning, placement, CTS, routing, timing closure, HBM
More semiconductor jobs: Micron Technology jobs · Physical design jobs · California jobs
First seen in our index 103 days ago, well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
721
|
Median days since first seen
61 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (721 roles · 88 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 721 |
| Open roles in the wider Physical Implementation family | 78 | 1646 · 118 employers |
| Median days since first seen | 89 d | 61 d (−28 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: floor-planning, placement, CTS, routing, timing closure, HBM
Who's hiring in this category
- Qualcomm · 108 open roles · median 60 d
- AMD · 64 open roles · median 43 d
- Broadcom · 48 open roles · median 34 d
- NVIDIA · 46 open roles · median 83 d
- Synopsys · 43 open roles · median 41 d
- Apple · 32 open roles · median 6 d
How we counted: 721 open Physical Design (Physical Design) roles from 88 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.