HBM Logic Architect
$150,000 - $320,000 USD yearly
Originally posted 28 July 2026 by the employer.
About the role
The HBM Logic Architect defines, designs, and validates digital IP for ASIC/SoC products, driving system-level co-optimization beyond standalone DRAM design. The role focuses on digital IP architecture, RTL design, and technical customer engagement for HBM development.
What you'll do
- Define, design, and validate digital IP for ASIC/SoC products.
- Perform RTL design and implementation based on approved specifications using industry-standard design methodologies.
- Review digital IP requirements, evaluate architecture options based on PPA targets, and determine implementation decisions.
- Provide design guidance and support for physical design implementation.
- Strengthen digital IP design capabilities for HBM and DRAM development through direct technical engagement with U.S.-based customers.
- Drive system-level co-optimization beyond standalone DRAM design.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
- Experience in high-speed digital PHY or high-speed IP design and analysis.
- Experience in DRAM memory controller design and analysis.
- Experience in DRAM DFT/DFD architecture, design, or analysis.
- Experience with PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design.
Nice to have
- Master’s degree in Electrical Engineering or a related discipline.
- Experience in PPA (Power, Performance, Area) optimization.
Skills: HBM architecture, 3D-stacked DRAM, RTL design, digital IP, memory controller design, DRAM DFT/DFD
More semiconductor jobs: San Jose jobs
This role has been open 97 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
311
|
Median days open
69 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (311 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 311 |
| Median days open | 97 d | 69 d (+28 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: HBM architecture, 3D-stacked DRAM, RTL design, digital IP, memory controller design, DRAM DFT/DFD
Who's hiring in this category
- Micron Technology · 160 open roles · median 79 d
- Synopsys · 32 open roles · median 74 d
- Qualcomm · 19 open roles · median 95 d
- Broadcom · 16 open roles · median 75 d
- SanDisk · 15 open roles · median 4 d
- NVIDIA · 8 open roles · median 56 d
How we counted: 311 open Memory Design (Memory Design) roles from 30 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.