Hardware Verification Engineer - Austin, Texas, United States
Originally posted 25 March 2026 by the employer.
About the role
The Hardware Verification Engineer builds testbenches and writes test sequences for complex IPs. The position focuses on verifying configurable interconnect IP for SoC, chiplet, and multi-chiplet systems.
What you'll do
- Create test plans for highly configurable IPs providing interconnectivity across an SoC, chiplet, or multi-chiplet systems. - Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboards. - Collaborate with software teams to define and implement configurable testbenches. - Work directly with design teams on test plans, failure debug, and coverage.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or Computer Science. - 8+ years of current hands-on experience in block-level, IP-level, or SoC-level verification. - Proficiency in Verilog and SystemVerilog. - Familiarity with industry-standard EDA tools for simulation and debug. - Deep experience with UVM-based testbenches. - Experience with modern programming languages like Python. - Knowledge of Arm AMBA protocols such as AXI, APB, and AHB. - Experience working with IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs.
Nice to have
- Understanding of Arm CHI protocol. - Experience with formal verification techniques and emulation platforms.
Skills: UVM/SystemVerilog, test plan, testbenches, SoC-level verification, Arm AMBA protocols
This role has been open 88 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Baya Systems | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1201 |
| Open roles in the wider Digital Design & Verification family | 11 | 3224 · 116 employers |
| Median days open | 88 d | 66 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM/SystemVerilog, test plan, testbenches, SoC-level verification, Arm AMBA protocols
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.