Hardware Test Engineer - Mountain View, CA, United States
$145,000 USD yearly
Originally posted 18 June 2026 by the employer.
Join DensityAI to own the test of our AI accelerator hardware.
About the role
This role involves owning the test strategy for DensityAI's AI accelerator hardware, spanning package, board, and full system levels.
What you'll do
- Develop and run package-level test including power-up, interface/interconnect continuity, and functional/parametric checks.
- Develop and run board-level test, including functional, structural (boundary scan/JTAG), in-circuit, and bring-up validation.
- Build out system-level test, bringing up and validating assembled accelerator systems with functional, stress, and burn-in flows.
- Design and validate test hardware and fixtures such as sockets, connectors, load boards, and board/system fixtures.
- Drive test coverage, yield analysis, and test-time/cost reduction across the product lifecycle.
- Lead new-product test bring-up and resolve test escapes, yield excursions, and hardware failures with data-driven root cause.
What you'll need
- BS/MS in Electrical/Computer Engineering or equivalent with 5+ years in package/board/system-level hardware test engineering.
- Hands-on test experience across at least two of package-level, board-level, and system-level test.
- Package and board test hardware experience (sockets, connectors, load boards, fixtures) with high-speed, high-current test considerations.
- Lab bring-up and debug skills including oscilloscopes, logic and protocol analyzers, power and thermal instrumentation.
- Data analysis and statistical skills for yield, characterization, and correlation work.
Nice to have
- High-speed I/O / SerDes, DDR/HBM, RF, or high-current/power-device test.
- Structural test (boundary scan).
- Scripting/automation (Python, C++).
- System burn-in and reliability test.
- OSAT/CM partner management.
This role has been open 34 days — slightly above the 28-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
542
|
Median days open
28 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (542 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 542 |
| Open roles in the wider Silicon Validation & Test family | 2 | 2224 · 112 employers |
| Median days open | 34 d | 28 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Who's hiring in this category
- Teradyne · 72 open roles · median 27 d
- Renesas Electronics · 45 open roles · median 22 d
- Infineon Technologies · 41 open roles · median 37 d
- Micron Technology · 27 open roles · median 35 d
- Qualcomm · 27 open roles · median 27 d
- AMD · 25 open roles · median 42 d
How we counted: 542 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.