Hardware Technical Program Manager
$200,000 - $240,000 USD yearly
Originally posted 14 August 2026 by the employer.
About the role
This role involves owning the program end-to-end, from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release for the Electron E1 processor.
What you'll do
- Own the silicon schedule from architecture freeze through tapeout, bring-up, and production.
- Drive the weekly execution cadence, including program reviews, design reviews, and tapeout readiness.
- Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software teams.
- Manage dependency chains for hardware programs, including IP delivery, PDK/library releases, EDA versions, and emulation capacity.
- Run the tapeout checklist and signoff matrix, holding owners to closure criteria.
- Interface with foundry, OSAT, IP, and EDA partners on deliverables and escalations.
What you'll need
- B.S. in Electrical/Computer Engineering, Computer Science, or equivalent.
- 7+ years in semiconductor/hardware engineering or program management.
- At least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up.
- Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation.
- Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping.
- Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem.
Nice to have
- Prior hands-on engineering experience in design, DV, or physical design.
- Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC).
- Familiarity with AI/ML accelerators, dataflow or novel compute architectures.
- Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines.
- Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination.
- Experience with EVK/reference board programs and customer/FAE enablement schedules.
- Familiarity with quality and compliance frameworks relevant to the target market.
Skills: silicon schedule, tapeout, cross-functional execution, chip design flow, post-silicon validation
This role has been open 64 days — well above the 46-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
46 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 175 |
| Median days open | 76 d | 46 d (+30 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: silicon schedule, tapeout, cross-functional execution, chip design flow, post-silicon validation
Who's hiring in this category
- Qualcomm · 25 open roles · median 46 d
- NVIDIA · 20 open roles · median 34 d
- AMD · 19 open roles · median 25 d
- Synopsys · 14 open roles · median 46 d
- Arm Holdings · 10 open roles · median 83 d
- Astera Labs · 6 open roles · median 67 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.