Hardware System Diagnostic Engineer - Mountain View, CA, United States
$120,000 - $450,000 USD yearly
Originally posted 26 May 2026 by the employer.
Develop and own end-to-end diagnostics for accelerator boards and rack-scale AI hardware covering PCIe, HBM, power, and thermals.
About the role
The Hardware System Diagnostic Engineer defines, designs, and owns the end-to-end diagnostics test suite for manufacturing, debugging, and deployment of MatX's rack-scale AI data center product. This includes collaborating with JDM partners to ensure manufacturing yield across accelerator boards and rack-level systems.
What you'll do
- Own the end-to-end diagnostics test suite for accelerator boards and racks. - Develop diagnostic tools covering the AI chip, PCIe, HBM, power, and thermal. - Define test coverage and pass/fail criteria for manufacturing screening. - Enable JDM/ODM partners with documentation, tooling, and hands-on debug support through NPI and production ramp phases. - Triage and root-cause manufacturing test escapes and field failures. - Build and maintain CI/CD infrastructure for the diagnostics software stack while tracking yield, test coverage, and defect density metrics.
What you'll need
- 7+ years in systems diagnostics, hardware validation, or manufacturing test. - Expert-level Python and C/C++ skills for test automation and low-level device programming. - Deep knowledge of PCIe, memory hierarchies, power management, and I/O. - Proven experience managing test relationships with ODM/JDM or CM partners. - Demonstrated experience building and scaling test automation frameworks from the ground up. - Proficiency with Linux system tools for hardware interrogation and fault analysis.
Nice to have
- Experience with AI accelerator, GPU, or custom ASIC diagnostics. - Familiarity with HBM or advanced packaging (2.5D/3D) test considerations. - Exposure to rack-scale management protocols and interfaces including BMC, PDU, IPMI, or Redfish. - Experience writing diagnostics that run at bare-metal or pre-OS environments. - Familiarity with error injection frameworks and fault coverage analysis. - Prior NPI experience at a semiconductor or early-stage hardware startup. - Familiarity with Linux drivers, PCIe enumeration, or register-level programming.
Skills: diagnostics test suite, accelerator boards, HBM, manufacturing screening, root-cause manufacturing escapes
This role has been open 150 days — well above the 40-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
432
|
Median days open
40 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MatX | All employers we track in this specialty (432 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 432 |
| Open roles in the wider Silicon Validation & Test family | 6 | 2238 · 112 employers |
| Median days open | 88 d | 40 d (+48 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: diagnostics test suite, accelerator boards, HBM, manufacturing screening, root-cause manufacturing escapes
Who's hiring in this category
- AMD · 54 open roles · median 43 d
- Qualcomm · 38 open roles · median 30 d
- Micron Technology · 36 open roles · median 39 d
- NVIDIA · 26 open roles · median 25 d
- Microchip Technology · 22 open roles · median 75 d
- Apple · 20 open roles · median 2 d
How we counted: 432 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.