Hardware Engineering, Sr Staff Engineer- 19027 - Remote
Originally posted 28 September 2026 by the employer.
This role focuses on DDR/HBM SIPI engineering.
About the role
This role involves high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, and jitter, to create high-performance silicon chips.
What you'll do
- Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.
- Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.
- Assess power delivery systems to optimize power integrity for supply stability and jitter minimization.
- Document findings in reports and design guidelines.
- Communicate results and insights to design teams to improve PHY design.
- Communicate results and recommendations to customers to enable them to optimize their system performance.
- Interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems.
- Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.
- Track industry developments through activities at standards committees and through memory vendor roadmaps.
What you'll need
- Proven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
- Well-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
- Ability to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.
- Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
- Knowledgeable in board-level construction and on-chip IO design operation.
Skills: DDR/HBM SIPI, high-speed interface, signal integrity, power integrity, channel loss, equalization
This role has been open 16 days — well below the 70-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
70 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (238 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 45 | 1423 · 106 employers |
| Median days open | 31 d | 70 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: DDR/HBM SIPI, high-speed interface, signal integrity, power integrity, channel loss, equalization
Who's hiring in this category
- Synopsys (this employer) · 31 open roles · median 31 d
- AMD · 29 open roles · median 37 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 170 d
- Micron Technology · 14 open roles · median 54 d
- Apple · 12 open roles · median 17 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.