Skip to main content
Teradyne

Hardware Engineering Manager (MEMORY TEST DIVISION, San Jose, CA)

Teradyne San Jose, CA, United States 28 days ago
Verification, Validation & Test

$167,000 USD yearly

Originally posted 15 September 2026 by the employer.

About the role

This role involves leading a team of Product and Hardware Engineers to transition new semiconductor test platforms and hardware products from development into high-volume manufacturing.

What you'll do

  • Lead, mentor, and develop a team of Product and Hardware Engineers.
  • Drive New Product Introduction activities from design release through manufacturing ramp.
  • Partner with R&D, Manufacturing, Supply Chain, Quality, and Program Management teams.
  • Ensure product readiness for high-volume production, quality, reliability, and cost targets.
  • Lead root cause analysis and corrective actions for product and manufacturing issues.
  • Manage project schedules, risks, resource allocation, and executive status reporting.

What you'll need

  • Bachelor's degree in Electrical Engineering, Mechanical Engineering, or related field.
  • 10+ years of engineering experience in semiconductor test equipment, ATE, or semiconductor capital equipment.
  • 5+ years of people management experience leading engineering teams.
  • Proven experience taking products from development through high-volume manufacturing.
  • Strong knowledge of manufacturing processes, product qualification, DFM, reliability, and production ramp methodologies.

Nice to have

  • MS or MBA.
  • Experience with mixed-signal, power, digital, or precision instrumentation hardware.
  • Knowledge of FMEA, Lean Manufacturing, Six Sigma, and reliability engineering practices.
  • Experience supporting global manufacturing and supply chain operations.
Market context

This role has been open 25 days — below the 27-day median for Silicon Test Engineering roles.

Silicon Test Engineering · DFT Test

Open roles in category
526
Median days open
27 d
Median salary
$169k
See the full market breakdown ▾Category comparison, and who else is hiring
How Teradyne compares in Silicon Test Engineering hiring
Metric Teradyne All employers we track in this specialty (526 roles · 76 employers)
Open roles in this specialty 68 526
Open roles in the wider Silicon Validation & Test family 85 2199 · 111 employers
Median days open 25 d 27 d (−2 d vs this employer)
Median salary (USD postings) — $169k

Who's hiring in this category

  • Teradyne (this employer) · 67 open roles · median 25 d
  • Renesas Electronics · 41 open roles · median 25 d
  • Infineon Technologies · 39 open roles · median 35 d
  • Micron Technology · 28 open roles · median 34 d
  • AMD · 26 open roles · median 40 d
  • Qualcomm · 25 open roles · median 27 d

How we counted: 526 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

Apply now
San Jose, CA, United States
On-site
$167,000 USD yearly
28 days ago

Share this job