Hardware Engineer (Memory Test Division, San Jose, CA)
$135,000 - $216,000 USD yearly
Originally posted 22 July 2026 by the employer. Relisted by the employer on 17 September 2026.
About the role
As a Senior Hardware Engineer in the Memory Test Division, you will lead production test, hardware debug, manufacturing test development, yield and quality improvement, and cross-functional execution for new product introduction (NPI) and ongoing manufacturing operations.
What you'll do
- Lead testing, troubleshooting, and root-cause analysis of analog, digital, and mixed-signal circuits down to the component level using oscilloscopes, multimeters, power analyzers, logic analyzers, and automated test equipment. - Define, develop, and optimize manufacturing test strategies and processes for new and sustaining products at Contract Manufacturers. - Provide Design-for-Test (DFT) recommendations during product development and design reviews. - Analyze test yields, failure trends, and production data using pareto charts and technical summaries to drive corrective actions and long-term product reliability. - Develop, validate, and maintain test station procedures, documentation, preventive maintenance schedules, and escalation paths. - Serve as a senior technical resource, supporting NPI readiness activities, production ramps, and mentoring junior team members.
What you'll need
- B.S. in Engineering (Electrical Engineering, Engineering Technology, or a related discipline). - 8+ years of experience in test engineering, hardware engineering, manufacturing engineering, or manufacturing support for electronic products. - Advanced experience with PCB-level debug, mixed-signal electronics, embedded hardware, and component-level troubleshooting. - Demonstrated ability to develop, implement, and optimize manufacturing test processes for complex electronic products. - Proficiency with PC-based test systems, automated test equipment, and electrical instrumentation. - Experience analyzing production data, test yields, failure trends, and quality metrics to drive corrective actions. - Demonstrated ability to provide Design-for-Test (DFT) input and influence product readiness during NPI.
This role has been open 88 days — well above the 31-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
550
|
Median days open
31 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (550 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 78 | 550 |
| Open roles in the wider Silicon Validation & Test family | 95 | 2227 · 113 employers |
| Median days open | 26 d | 31 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne (this employer) · 75 open roles · median 25 d
- Renesas Electronics · 43 open roles · median 25 d
- Infineon Technologies · 41 open roles · median 41 d
- Micron Technology · 29 open roles · median 35 d
- Qualcomm · 28 open roles · median 31 d
- Texas Instruments · 23 open roles · median 26 d
How we counted: 550 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.