GSoC Design Verification Engineer
$98,500 - $147,700 USD yearly
Originally posted 10 August 2026 by the employer.
Work on AI-powered intelligent agents that assist engineers in Design Verification.
About the role
This role offers an opportunity to work on multi-core CPUs, cache coherency systems, memory subsystems, AI/ML accelerators, high-speed interconnects, and modern SoC architecture.
What you'll do
- Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
- Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
- Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
- Develop assertions, functional coverage models, and checkers.
- Debug RTL, testbench, and integration issues and work closely with design teams to resolve defects.
- Drive coverage closure using functional and code coverage metrics.
- Verify complex Data Center SoC features.
- Develop AI agents that automate engineering tasks across domains workflows.
What you'll need
- Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
- Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, System level Use case verification.
- Experience developing verification environments from architecture/specification through signoff.
- Strong understanding of computer architecture and digital design fundamentals.
- Experience debugging complex SoC-level issues.
- Proficiency in Python or scripting languages for automation.
- AI-assisted verification of workflows and test generation.
Nice to have
- Experience in full-chip or subsystem verification environments.
- Experience with one or more of the following: CPU verification, Cache coherency protocols (ACE, CHI, CXL), DDR or HBM memory systems, PCIe, Ethernet, or networking protocols, AI/ML accelerator verification, Security and RAS feature verification, System Power and Performance verification.
- Experience with: Portable Stimulus (PSS), Formal Verification, Emulation platforms (Veloce/Palladium/ZeBu), Power-aware verification.
- Understanding of machine learning and Generative AI concepts.
- Knowledge of LLMs such as GPT, Claude, Llama, or equivalent models.
Skills: System Verilog, UVM, verification plans, functional coverage, debug RTL, AI-powered intelligent agents
This role has been open 68 days — slightly above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1205
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1205 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 110 | 1205 |
| Open roles in the wider Digital Design & Verification family | 381 | 3202 · 115 employers |
| Median days open | 38 d | 64 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: System Verilog, UVM, verification plans, functional coverage, debug RTL, AI-powered intelligent agents
Who's hiring in this category
- Qualcomm (this employer) · 110 open roles · median 38 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 86 open roles · median 58 d
- Synopsys · 64 open roles · median 32 d
- SiFive · 55 open roles · median 74 d
- Cadence Design Systems · 50 open roles · median 116 d
How we counted: 1205 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.