GPU/SOC Low-Power Feature Architect - HSIO - CA, Santa Clara, United States
Originally posted 2 June 2026 by the employer — open 99 days.
This role focuses on advancements in NVLink and NVLink-C2C.
About the role
This role involves the architectural development and system integration of GPU/SOC low-power features within the HW ArchDev team. The position focuses on next-gen high-speed interconnects like NVLink and NVLink-C2C.
What you'll do
- Contribute to the design of high-speed IOs, including NVLink and NVLink-C2C.
- Optimize IO power and push energy efficiency.
- Ensure interoperability with connected devices and system components in complex interconnect topologies.
- Deep dive into HSIO bugs and drive debug efforts across various teams.
- Collaborate with system architects, mixed-signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams.
What you'll need
- BS or MS degree in EE/CE or equivalent experience.
- Minimum 10 years working on HSIO with experience in power management, use case analysis, perf/power modeling, bringup, and/or debug.
- Experience with system-level and interconnect power management optimizations.
- Experience with silicon and platform-level power modeling for active/idle use cases.
- Understanding of firmware/driver structures and their interaction with HW.
- Strong EE fundamentals.
- Knowledgeable in computer architecture, high-speed interfaces, timing analysis, process variations, statistical error rates, and power analysis.
Skills: high-speed IOs, NVLink, NVLink-C2C, IO power optimizations, interoperability, HSIO bugs, system-level and interconnect power management
This role has been open 178 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 10 | 217 |
| Median days open | 95 d | 91 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: high-speed IOs, NVLink, NVLink-C2C, IO power optimizations, interoperability, HSIO bugs
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA (this employer) · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.