Full Chip Timing Modeling and Integration Engineer - San Jose, California, United States
$133,200 - $192,825 USD yearly
Originally posted 11 October 2026 by the employer.
About the role
As a Full Chip Timing Modeling and Integration Engineer, you will develop timing methodologies and execute full-chip timing for Altera’s product lines.
What you'll do
- Develop timing methodologies and execute full-chip timing for FPGA products using advanced process technologies.
- Collaborate with cross-functional teams to define timing modeling strategies and solutions.
- Generate high-level timing models and perform timing model integration and validation.
- Perform full-chip timing analysis, including clocking and timing constraint development.
- Work with Front-End and Back-End design teams to understand design architecture and implementation.
- Debug and troubleshoot technical issues, including design issues, and proactively intervene to resolve them.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience in SoC development.
- 5+ years of industry experience working with advanced semiconductor process nodes.
- 5+ years of industry experience with industry-standard timing formats and design constraints, including Liberty, Verilog, and Synopsys Design Constraints (SDC).
- 5+ years of industry experience with Static Timing Analysis (STA), including correlating STA results with SPICE.
- 5+ years of industry experience in timing modeling and library quality assurance (QA).
- 5+ years of industry experience writing Python and Tcl scripts for design automation.
- 5+ years of industry experience applying silicon modeling concepts, such as LVF and POCV.
Nice to have
- 7+ years of relevant industry experience.
- Experience completing complex designs involving multiple voltage domains.
- Experience with common modes of operation, including functional and Design-for-Test (DFT), for use in timing constraint review and management.
- Experience in the architecture and/or design of FPGA, DDR, PCIe, or related technologies.
- Experience applying AI/ML techniques to improve and optimize execution.
Skills: FPGA, full-chip timing, timing analysis, SDC, Static Timing Analysis, timing modeling
This role has been open 0 days — well below the 53-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
104
|
Median days open
53 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (104 roles · 27 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 104 |
| Median days open | 53 d | 53 d (same as this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: FPGA, full-chip timing, timing analysis, SDC, Static Timing Analysis, timing modeling
Who's hiring in this category
- Altera (this employer) · 30 open roles · median 53 d
- AMD · 11 open roles · median 48 d
- Teradyne · 10 open roles · median 63 d
- Qualcomm · 8 open roles · median 35 d
- Microchip Technology · 6 open roles · median 86 d
- Infineon Technologies · 4 open roles · median 31 d
How we counted: 104 open FPGA Design (RTL Design) roles from 27 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.