Full Chip Timing Lead - Hyderabad-Sattva, India
Originally posted 15 September 2026 by the employer — open 5 days.
About the role
This role involves ownership of SoC Full Chip Timing closure, including high-frequency CPU, HBM, DDR, and Serdes interfaces, with responsibility for SDC validation and timing signoff execution.
What you'll do
- Own Full chip Timing Closure.
- Provide Clock build guidance using MSCTS and Mesh methods.
- Drive new improvements in timing closure.
- Analyze data and provide feedback to the PnR execution team.
- Drive the common STA methodology in the business unit.
- Work with CAD and central methodology teams to drive requirements.
What you'll need
- 8+ years of experience in design signoff closure.
- Timing closure experience at SoC and block level.
- Technical depth in STA and High freq interface closure in hierarchical STA.
- Experience with Multi voltage closure.
- Strong SDC coding and debug skills.
- Scripting language experience: TCL, Perl, Python, Makefile.
Nice to have
- Timing ECO flow experience.
- Hyperscale, Yield analysis experience.
- PnR and STA signoff correlation drive and convergence experience.
- Experience in deploying and implementing ML techniques and algorithms in physical design.
- Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification.
- Experience with Synopsys, Cadence and Mentor tools.
- AMD block TileBuilder and experience in lower tech nodes (5/3/2).
Skills: Full chip Timing closure, STA, SDC, PnR, physical verification
This role has been open 5 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
604
|
Median days open
59 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (604 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 604 |
| Open roles in the wider Physical Implementation family | 59 | 1373 · 107 employers |
| Median days open | 39 d | 59 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Full chip Timing closure, STA, SDC, PnR, physical verification
Who's hiring in this category
- Qualcomm · 108 open roles · median 42 d
- NVIDIA · 39 open roles · median 44 d
- Broadcom · 38 open roles · median 69 d
- AMD (this employer) · 35 open roles · median 39 d
- Synopsys · 27 open roles · median 58 d
- Renesas Electronics · 25 open roles · median 46 d
How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.