FPGA System Design Engineer - San Jose, California, United States
$118,900 - $172,200 USD yearly
Originally posted 13 August 2026 by the employer.
Work with Altera FPGA platforms to architect and implement advanced signal processing and embedded computing solutions.
About the role
As an FPGA System Design Engineer, you will join the Aerospace, Defense, and Government (ADG) solutions team to architect, implement, optimize, and benchmark advanced signal processing and embedded computing solutions on Altera FPGA platforms. This role focuses on FPGA-based DSP, embedded systems, AI inference, high-speed data converters, and advanced RF signal processing applications.
What you'll do
- Design, develop, and implement FPGA-based solutions using RTL, DSP Builder, and embedded processor technologies for defense and aerospace applications.
- Partner with strategic customers to deploy and optimize DSP, communications, AI, and signal processing algorithms on Altera FPGA devices.
- Develop benchmarks, proof-of-concept demonstrations, and reference designs that showcase FPGA performance and value.
- Collaborate with FPGA software and tools teams to identify customer needs and drive tool enhancements.
- Analyze system-level performance and optimize FPGA implementations for throughput, latency, power, and resource utilization.
- Support customer design activities including architecture reviews, debugging, performance tuning, and technical enablement.
- Contribute technical collateral including design documentation, application notes, training materials, and best-practice guides.
What you'll need
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 3+ years of experience in FPGA design and algorithm implementation.
- 2+ years of software development experience using C/C++.
- 1+ year of FPGA development experience using Verilog or VHDL.
- Strong understanding of digital logic design and FPGA development methodologies.
- Experience debugging and validating complex hardware/software systems.
- Eligibility to obtain and maintain a U.S. Government security clearance.
Nice to have
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Hands-on experience with MATLAB and Simulink.
- Hands-on experience with C/C++ and CUDA.
- Hands-on experience with Verilog and/or VHDL FPGA design.
- Hands-on experience with Quartus® Prime and ModelSim™/Questa™ simulation tools.
- Hands-on experience with Real-Time Operating Systems (RTOS).
- Background in Digital Signal Processing (DSP).
- Background in Signal and Image Processing.
- Background in Wireless and Communication Systems.
- Background in Artificial Intelligence and Deep Learning.
- Background in High-speed ADC/DAC architectures.
- Background in RF and Software Defined Radio (SDR) systems.
- Experience with FPGA SoCs, embedded processors, and heterogeneous computing architectures.
This role has been open 65 days — slightly above the 60-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
102
|
Median days open
60 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (102 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 102 |
| Median days open | 59 d | 60 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera (this employer) · 30 open roles · median 59 d
- AMD · 12 open roles · median 50 d
- Teradyne · 10 open roles · median 69 d
- Qualcomm · 8 open roles · median 41 d
- Microchip Technology · 6 open roles · median 92 d
- Infineon Technologies · 4 open roles · median 37 d
How we counted: 102 open FPGA Design (RTL Design) roles from 26 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.