FPGA Prototyping Lead - CA, San Jose, United States
$175,000 - $300,000 USD yearly
Originally posted 20 July 2026 by the employer.
About the role
As a member of the front-end design and integration team, you will drive FPGA prototyping strategy and execution for complex SoCs to enable first-pass silicon success. You will work closely with Architecture, IP Design, Physical Design, Verification, Software, and Product Engineering teams.
What you'll do
- Define and own the FPGA prototyping architecture, methodology roadmap, and platform strategy for complex SoCs, including partitioning, interconnects, clocking, debug infrastructure, and high-speed interfaces. - Lead the development and deployment of FPGA prototype platforms, including RTL adaptation, implementation flows, verification infrastructure, regression environments, and system-level debug capabilities. - Drive collaboration across Architecture, RTL Design, Verification, Emulation, Software, and Firmware teams to enable early hardware validation, software bring-up, and functional coverage goals. - Provide technical leadership for FPGA prototyping engineers through mentoring, design reviews, best-practice development, project planning, and execution of program milestones. - Establish engineering processes, implementation methodologies, documentation standards, and continuous improvement initiatives. - Represent the FPGA prototyping organization in architecture reviews, program reviews, and customer-facing technical discussions while partnering with EDA and FPGA tool vendors.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Nice to have
- 12+ years of experience in FPGA design, implementation, and SoC prototyping. - Proven experience leading FPGA prototyping efforts for large-scale semiconductor programs. - Hands-on experience with Synopsys HAPS and/or Cadence Protium platforms. - Strong knowledge of multi-FPGA partitioning, board bring-up, and high-speed interfaces such as PCIe, DDR, Ethernet, USB, and HBM. - Expert proficiency with AMD/Xilinx Vivado and Vitis toolchains. - Deep expertise in FPGA timing closure, floorplanning, CDC analysis, pipelining, and performance optimization. - Strong SystemVerilog and/or Verilog design and verification experience. - Solid understanding of modern SoC architectures, including CPUs, cache hierarchies, memory subsystems, NoC/interconnects, and I/O protocols such as AXI, ACE, CHI, PCIe, and DDR.
This role has been open 92 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 71 | 1051 |
| Open roles in the wider Digital Design & Verification family | 253 | 3261 · 116 employers |
| Median days open | 42 d | 62 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD (this employer) · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.