FPGA Engineering Manager (MTD, San Jose, CA)
$171,000 - $273,600 USD yearly
Originally posted 13 July 2026 by the employer.
About the role
Teradyne's Memory Test Division (MTD) is seeking a hands-on FPGA Engineering Manager to oversee the development of memory test solutions and lead a team of 4 to 6 engineers. The role combines technical oversight, project management, and direct engineering contributions to test instrumentation incorporating digital, analog, ASIC, FPGA, and liquid cooling technologies.
What you'll do
- Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope while representing the team at program reviews. - Provide hands-on technical guidance by reviewing and contributing to FPGA architectures, designs, and specifications. - Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation. - Work closely with hardware, software, and firmware engineers to ensure integration of FPGA designs into larger systems, and provide support for sustaining issues. - Recruit, onboard, retain engineering talent, set goals, and conduct regular performance reviews for an engineering team. - Contribute to FPGA team process improvement initiatives.
What you'll need
- B.S. or M.S. in Electrical Engineering or closely related discipline. - 12+ years of relevant experience in digital ASIC or FPGA design. - Minimum of 5 years of experience as an FPGA/ASIC project lead driving projects through concept development, architectural exploration, design implementation, lab validation, and production release. - Extensive experience coding RTL (Verilog preferred), using digital simulation tools (Cadence preferred), and using static timing analysis tools. - Experience designing with PCIe, DDR3/4/5, AXI, Ethernet, SPI, and SERDES. - Experience with AMD or Altera FPGAs and development tools (Vivado/Quartus), as well as digital design quality tools including Lint and CDC. - Experience with source control systems, continuous integration, bug tracking tools, and project scheduling tools. - Familiarity with digital verification tools and methodologies (preferably UVM).
Nice to have
- Experience developing hardware for automated test equipment. - Experience as a first level manager of an engineering team. - Experience with FPGA transceiver based designs. - Experience with DRAM and Flash memory interfaces. - Experience with Linux and Windows operating systems. - Familiarity with ATE instrumentation.
Skills: FPGA, test and automation, next-generation technologies, solutions, manufacturing automation
This role has been open 99 days — well above the 63-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
100
|
Median days open
63 d
|
Median salary
$163k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (100 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 100 |
| Median days open | 73 d | 63 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Skills observed across this category: FPGA, test and automation, next-generation technologies, solutions, manufacturing automation
Who's hiring in this category
- Altera · 30 open roles · median 59 d
- AMD · 11 open roles · median 57 d
- Teradyne (this employer) · 10 open roles · median 72 d
- Qualcomm · 8 open roles · median 44 d
- Microchip Technology · 6 open roles · median 95 d
- Infineon Technologies · 4 open roles · median 40 d
How we counted: 100 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.