$123,100 - $196,900 USD yearly
Architect and implement FPGA solutions to support Flash and DRAM test instrumentation in the Memory Test Division.
Originally posted 10 November 2026 by the employer.
About the role
Teradyne's Memory Test Division (MTD) seeks an FPGA Design Engineer to support the development of memory test solutions. The role involves designing FPGA implementations for Flash and DRAM test instrumentation.
What you'll do
- Architect and implement FPGA solutions to support Flash and DRAM test instrumentation.
- Provide technical guidance to junior engineers.
- Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
- Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
- Maintain schedule commitments and deliver high quality end products.
What you'll need
- Bachelor's Degree in Electrical Engineering or a closely related field with a minimum of 5 years of relevant work experience, or a Master's Degree with a minimum of 3 years of relevant work experience.
- Experience with Digital Design and Architecture.
- Experience with RTL coding, synthesis, timing closure, and lab validation.
- Experience with Static Timing Analysis of ASICs or FPGAs.
- Experience with digital simulation testbench creation.
- Experience with C or C++.
- Familiarity with lab equipment such as oscilloscopes, power supplies, and waveform generators.
Nice to have
- FPGA Transceiver based design experience.
- Experience with DRAM and Flash Memory interfaces.
- Experience with Altera/AMD FPGA tool flows.
- Proficiency with Verilog HDL Language.
- Familiarity with UVM Methodology.
- Scripting languages experience.
- Linux and Windows operating systems experience.
- Familiarity with ATE instrumentation.
More semiconductor jobs: Teradyne jobs · FPGA engineer jobs · Oregon jobs
First seen in our index 3 days ago, well below the 64-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
106
|
Median days since first seen
64 d
|
Category median salary (all employers)
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (106 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 106 |
| Median days since first seen | 73 d | 64 d (−9 d vs this employer) |
| Median salary (USD postings) | n/a | $162k |
Who's hiring in this category
- Altera · 37 open roles · median 61 d
- Teradyne (this employer) · 10 open roles · median 73 d
- AMD · 9 open roles · median 72 d
- Keysight Technologies · 7 open roles · median 21 d
- Microchip Technology · 6 open roles · median 95 d
- Qualcomm · 6 open roles · median 69 d
How we counted: 106 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.