Originally posted 10 November 2026 by the employer.
About the role
As an FPGA Design and Timing Modeling Engineer, you will translate the behavior and performance of AMD FPGA hardware into accurate timing models used by Vivado to compile, analyze, and optimize customer designs. You will investigate differences between simulated, modeled, and measured silicon performance across FPGA circuit design, silicon characterization, and software device modeling.
What you'll do
- Generate simulation based delays using existing hardware designs to match FPGA timing arcs as per the device model.
- Develop automation flows to improve FPGA timing quality.
- Drive silicon based characterization of FPGA resources and root cause mis-correlation with the expected timing model.
- Conduct performance analysis on complex designs using the Vivado tool.
- Coordinate release readiness reviews and manage risk mitigation plans to enable successful production release of Vivado timing.
- Train junior team members and deliver on time results with quality.
What you'll need
- Bachelor's or Master's degree in Computer Science or Electrical Engineering.
- Understanding of digital circuits, FPGA device architecture, and programmable logic architecture.
- Experience with timing analysis, simulation, and silicon characterization.
- Experience working with cross-functional teams including front-end design, circuit design, custom layout design, place and route, and device modeling.
Nice to have
- Digital circuit design and FPGA device architecture experience.
- FPGA design implementation and performance analysis.
- Static Timing Analysis and timing-model fundamentals.
- Experience with PrimeTime, SPICE, and Vivado.
- CAD or engineering flow development.
- Python, Tcl, Perl, databases, and software algorithms.
- FPGA device modeling, timing characterization, or speed-file experience.
More semiconductor jobs: AMD jobs · FPGA engineer jobs · California jobs
First seen in our index 0 days ago, well below the 67-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
106
|
Median days since first seen
67 d
|
Category median salary (all employers)
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (106 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 106 |
| Median days since first seen | 73 d | 67 d (−6 d vs this employer) |
| Median salary (USD postings) | n/a | $162k |
Who's hiring in this category
- Altera · 36 open roles · median 59 d
- AMD (this employer) · 13 open roles · median 68 d
- Teradyne · 8 open roles · median 93 d
- Keysight Technologies · 7 open roles · median 17 d
- Qualcomm · 6 open roles · median 65 d
- Microchip Technology · 5 open roles · median 94 d
How we counted: 106 open FPGA Design (RTL Design) roles from 24 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.