FPGA Design and Test Engineer, Sr Staff

Originally posted 3 September 2026 by the employer.

Work on HAPS prototyping platforms that enable real customer designs to run before silicon exists.

About the role

This role involves developing and validating FPGA-optimized implementations for HAPS platforms, addressing challenges related to capacity limits, timing constraints, and multi-FPGA partitioning. You will directly affect how quickly customers can validate their next chip by working on real systems with hard problems.

What you'll do

• Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges.
• Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.
• Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues.
• Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins.
• Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries.
• Debug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers.

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of hands-on FPGA and RTL design experience.
• Expert-level proficiency in SystemVerilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis.
• Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion.
• Strong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug utilities, and engineering tools.
• Proficiency using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and multimeters to debug and validate hardware systems.

Skills: FPGA-optimized implementations, Vivado synthesis, place-and-route, timing closure, SystemVerilog, hardware validation