FPGA Compiler (Placer) Engineer - San Jose, California, United States
$149,100 - $215,900 USD yearly
Originally posted 23 June 2026 by the employer.
About the role
Altera is seeking an FPGA Compiler Engineer (Placer) to develop and optimize FPGA placement algorithms within the compiler toolchain in San Jose, CA.
What you'll do
- Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization. - Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams. - Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs. - Develop and refine timing-aware placement strategies to support high-frequency designs. - Analyze placement quality, congestion hotspots, and timing bottlenecks to drive improvements in convergence and design closure. - Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 6+ years of experience in FPGA/ASIC CAD, EDA tools, or related fields. - Experience with algorithms and data structures covering optimization, graph theory, and heuristics. - Experience with placement algorithms or physical design flows. - Experience in C/C++ and software engineering best practices. - Experience with placement techniques such as analytical placement, simulated annealing, partitioning, and clustering. - Experience with timing-driven and congestion-driven optimization.
Nice to have
- Experience with FPGA toolchains such as Quartus or Vivado. - Knowledge of FPGA architectures and interconnect fabrics. - Familiarity with routing and timing closure techniques. - Experience with parallel or distributed algorithms for EDA tools. - Scripting experience in Python or Tcl for tooling and automation.
This role has been open 120 days — well above the 64-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
101
|
Median days open
64 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (101 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 32 | 101 |
| Median days open | 57 d | 64 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera (this employer) · 31 open roles · median 57 d
- AMD · 11 open roles · median 59 d
- Teradyne · 9 open roles · median 74 d
- Qualcomm · 8 open roles · median 46 d
- Microchip Technology · 6 open roles · median 97 d
- Analog Devices · 4 open roles · median 97 d
How we counted: 101 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.