Foundation IP Design Verification Intern (Summer 2027)
$20 - $40 USD yearly
Originally posted 16 October 2026 by the employer.
About the role
This internship supports design verification for standard-cell libraries, memories, block-level IP, and chip-level integration across GlobalFoundries technologies. It involves hands-on experience with circuit and logic simulation, formal verification, post-silicon analysis, and silicon debug.
What you'll do
- Perform circuit and logic design verification using SPICE and Verilog simulation.
- Support verification of Foundation IP, including standard-cell libraries, memories, block-level IP, and chip-level integration.
- Use AI-assisted methods and engineering data to support performance prediction for Foundation IP.
- Contribute to formal verification activities and analyze verification results.
- Assist with post-silicon analysis and silicon debug for applicable Foundation IP.
- Develop scripts and use CAD tools to automate VLSI design, verification, analysis, and reporting tasks.
- Document methods, results, issues, and recommendations, and communicate findings to the engineering team.
What you'll need
- Actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Science, or a related field.
- At least a sophomore at the time of application.
- Overall 3.0 GPA or higher.
- English language fluency (written and verbal).
- Ability to work at least 40 hours per week during the internship.
Nice to have
- Prior related internship or co-op experience.
- Coursework or project experience in VLSI design, digital logic, circuit simulation, or semiconductor devices.
- Familiarity with SPICE, Verilog, formal verification, or electronic design automation tools.
- Experience with Python, Perl, Tcl, Shell, or a similar scripting language.
- Interest in AI-assisted engineering methods, performance modeling, post-silicon analysis, or silicon debug.
Skills: circuit verification, logic design verification, SPICE, Verilog simulation, formal verification, post-silicon analysis
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1195 |
| Open roles in the wider Digital Design & Verification family | 42 | 3198 · 115 employers |
| Median days open | 102 d | 64 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: circuit verification, logic design verification, SPICE, Verilog simulation, formal verification, post-silicon analysis
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.