Formal Verification Senior Engineer - Qualcomm, Cambridge, UK
Originally posted 4 September 2026 by the employer — open 13 days.
About the role
This role involves the formal property verification of 3D Graphics hardware pipelines, feature sets, data paths, and interfaces.
What you'll do
- Develop Formal Property Verification (FPV) test-plans.
- Develop assertion-based verification testbenches.
- Debug RTL artifacts.
- Achieve formal sign-off matrices.
- Collaborate with global GPU RTL design and DV teams.
- Achieve coverage closure.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience, or a Master's degree in Science, Engineering, or a related field and 1+ year of experience, or a PhD in Science, Engineering, or a related field.
- 2 years of relevant experience in Formal Verification.
- Hands-on experience in strategizing, brainstorming, and developing Formal Property Verification (FPV) test-plan.
- Hands-on experience writing SystemVerilog Assertions.
- Experience with industry standard formal tools.
- Experience solving formal proof complexity by applying various abstraction techniques.
- Experience with deep bug-hunting.
Nice to have
- Prior knowledge of GPU Architecture.
- Hands-on experience in other formal applications like DPV, C2RTL SEQ, RTL2RTL SEQ.
Skills: Formal Verification, FPV, SystemVerilog Assertions, JasperGold, VC Formal
This role has been open 13 days — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1122
|
Median days open
56 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1122 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 107 | 1122 |
| Open roles in the wider Digital Design & Verification family | 372 | 3007 · 114 employers |
| Median days open | 50 d | 56 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: Formal Verification, FPV, SystemVerilog Assertions, JasperGold, VC Formal
Who's hiring in this category
- Qualcomm (this employer) · 104 open roles · median 53 d
- AMD · 99 open roles · median 33 d
- NVIDIA · 90 open roles · median 65 d
- Micron Technology · 56 open roles · median 96 d
- Synopsys · 54 open roles · median 23 d
- SiFive · 51 open roles · median 44 d
How we counted: 1122 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.