Formal Design Verification Engineer - TX, Austin, United States
$126,700 - $217,200 USD yearly
Originally posted 9 April 2026 by the employer.
Focus on Central Verification R&D developing Formal Verification (FV) flows, methodologies, and model checking techniques.
About the role
AMD is seeking an engineer to join the Central Verification team focusing on Formal Verification (FV) flows and methodologies. The team serves as a central R&D group working across project execution teams to deliver design verification solutions.
What you'll do
- Contribute to products, flows, and methodologies that support extensive and efficient use of formal verification across AMD. - Drive or support projects applying formal verification, tools, and techniques to improve hardware design and implementation quality. - Identify, evaluate, and facilitate the deployment of verification solutions available inside and outside the company. - Share knowledge across global teams through hands-on work, documentation, and technical presentations.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. - Programming, scripting, and debugging skills. - Hands-on experience using formal verification tools from EDA vendors. - Knowledge of or experience with static analysis and/or formal methods, including formal logic and model checking. - Ability to understand hardware description languages and hardware design.
Nice to have
- Experience with data analysis, data mining, and machine learning. - Experience with cloud computing.
Skills: Formal Verification (FV), formal verification tools, static analysis, formal methods, hardware description languages
This role has been open 173 days — well below the 214-day median for Design Verification roles.
Design Verification · EDA Tools
|
Open roles in category
25
|
Median days open
214 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (25 roles · 8 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 25 |
| Open roles in the wider Digital Design & Verification family | 251 | 3310 · 115 employers |
| Median days open | 173 d | 214 d (−41 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Formal Verification (FV), formal verification tools, static analysis, formal methods, hardware description languages
Who's hiring in this category
- Cadence Design Systems · 13 open roles · median 214 d
- NVIDIA · 3 open roles · median 223 d
- Qualcomm · 3 open roles · median 199 d
- AMD (this employer) · 2 open roles · median 172 d
- Ahead Computing · 1 open role · median 194 d
- Astera Labs · 1 open role · median 223 d
How we counted: 25 open Design Verification (EDA Tools) roles from 8 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.