FEOL RET Process Development Engineer - Dallas, TX, United States
Originally posted 31 August 2026 by the employer.
About the role
This role involves translating customer design intent into manufacturable layouts by applying advanced retargeting techniques. You will optimize physical layouts for yield, performance, and manufacturability across various technology nodes, specifically for 28nm/22nm nodes.
What you'll do
- Develop and implement design retargeting strategies to bridge the gap between design intent and process capabilities.
- Collaborate with OPC, lithography, and process integration teams to ensure accurate pattern transfer and high-yield manufacturing.
- Analyze and modify layout geometries to improve printability and process window robustness.
- Work with EDA tools to automate retargeting flows and integrate them into the tape-out pipeline.
- Perform data analysis using CD metrology, SEM review, and simulation results to refine retargeting rules.
- Contribute to the development of design rules and patterning strategies for advanced nodes (e.g., 28nm, 22nm).
What you'll need
- Master's in Electrical Engineering, Physics, Materials Science, or a related field.
- 5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
- Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
- Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion).
- Proficiency in scripting with any scripting languages.
- Familiarity with layout editing and verification tools (e.g., Calibre, Virtuoso, ICC2).
- Understanding of lithography, patterning, and process integration challenges in advanced nodes, including 28nm and below.
Nice to have
- PhD in Electrical Engineering, Physics, Materials Science, or a related field.
- Solid knowledge of semiconductor device physics and fabrication processes.
- Experience in analog layout interaction with lithography and OPC flows.
- Experience with statistical data analysis and yield improvement methodologies.
- Knowledge of design rule checking (DRC) and layout versus schematic (LVS).
- Knowledge of Design Technology Co-Optimization (DTCO).
- Exposure to machine learning or data-driven approaches for layout optimization.
Skills: Design Retargeting, RET, OPC, lithography, process window robustness
This role has been open 43 days — well below the 61-day median for Process Engineering roles.
Process Engineering · Lithography Systems
|
Open roles in category
47
|
Median days open
61 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (47 roles · 13 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 47 |
| Open roles in the wider Process, Fab & Equipment family | 242 | 9855 · 109 employers |
| Median days open | 81 d | 61 d (+20 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Design Retargeting, RET, OPC, lithography, process window robustness
Who's hiring in this category
- Micron Technology · 26 open roles · median 71 d
- GlobalFoundries · 5 open roles · median 36 d
- Coherent Corp · 2 open roles · median 64 d
- SkyWater Technology · 2 open roles · median 51 d
- Skyworks · 2 open roles · median 160 d
- STMicroelectronics · 2 open roles · median 35 d
How we counted: 47 open Process Engineering (Lithography Systems) roles from 13 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.