Fellow Architect, Functional & Performance Verification - CA, San Jose, United States
Originally posted 3 August 2026 by the employer.
About the role
This Fellow-level architect role leads the evolution of pre-silicon verification and validation strategy within AMD's Adaptive and Embedded Computing Group (AECG), spanning IP, subsystem, and SoC development.
What you'll do
- Drive the definition, development, and execution of functional and performance verification and validation strategies, including verification planning, testbench architecture, and coverage closure across IP, subsystem, and SoC programs.
- Lead the evolution of simulation-based verification methodologies, encompassing constrained-random, directed, and coverage-driven approaches, while advancing formal, power, performance, and implementation verification strategies.
- Lead the evolution of firmware-based validation strategies and methodologies across prototyping and emulation platforms.
- Influence and shape the evolution of verification methodologies by working closely with AECG executives and senior leaders.
- Serve as a technical mentor and trusted advisor to verification engineers across AECG, elevating organizational expertise.
What you'll need
- Drive the definition, development, and execution of functional and performance verification and validation strategies, including verification planning, testbench architecture, and coverage closure across IP, subsystem, and SoC programs.
- Lead the evolution of simulation-based verification methodologies, encompassing constrained-random, directed, and coverage-driven approaches, while advancing formal, power, performance, and implementation verification strategies.
- Lead the evolution of firmware-based validation strategies and methodologies across prototyping and emulation platforms.
- Influence and shape the evolution of verification methodologies by working closely with AECG executives and senior leaders.
- Serve as a technical mentor and trusted advisor to verification engineers across AECG, elevating organizational expertise.
Nice to have
- Expert in programming and scripting languages such as C/C++, Python, Perl, and Ruby, along with strong proficiency in HDL/Verilog and UVM-based verification methodologies.
- Expert understanding of functional and performance verification tools, technologies, and solutions offered by leading EDA vendors (Synopsys, Cadence Design, Siemens).
- Deep background in architecting, developing, and deploying advanced functional verification and validation methodologies, frameworks, and environments for complex semiconductor designs.
- Hands-on experience with pre-silicon prototyping and emulation platforms and their application to functional and performance verification.
- Established record of technical thought leadership through publications, technical papers, patents, and presentations at internal and external conferences.
Skills: pre-silicon verification, UVM, testbench architecture, constrained-random, coverage-driven
This role has been open 76 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 95 | 1202 |
| Open roles in the wider Digital Design & Verification family | 251 | 3201 · 115 employers |
| Median days open | 52 d | 65 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: pre-silicon verification, UVM, testbench architecture, constrained-random, coverage-driven
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD (this employer) · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.