Define AI-assisted methodologies for generating synthesizable RTL from programmable packet-processing pipelines into Enterprise NIC and DPU silicon.
Originally posted 11 November 2026 by the employer.
About the role
AMD is seeking a Fellow to lead the development of AI-native methodologies for silicon architecture, RTL generation, verification automation, and design optimization. The role combines networking and ASIC architecture expertise with AI systems to transform programmable architectures into optimized fixed-function silicon for Enterprise NIC, DPU, and embedded networking programs.
What you'll do
- Define and lead AI-assisted methodologies for generating synthesizable RTL from high-level architectural specifications and programmable packet-processing pipelines.
- Develop automated techniques to optimize pipeline organization, lookup structures, memories, and datapaths for power, performance, area, and cost.
- Drive AI-assisted hardware architecture exploration, implementation, design optimization, and automated verification generation including reference models, testbenches, assertions, and coverage plans.
- Establish methodologies to prove functional equivalence between programmable and generated implementations using simulation, formal verification, and differential testing.
- Guide architectural tradeoffs across multiple ASIC programs, influencing future networking IP, Enterprise NIC, DPU, NoC technologies, telemetry, and infrastructure acceleration.
- Define reusable AI frameworks and scalable software infrastructure for architecture, design, verification, debug, and optimization workflows.
What you'll need
- PhD or equivalent industry experience in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
- Technical leadership experience across ASIC architecture, networking architectures, programmable packet processing, verification, and silicon design.
- Expertise spanning networking silicon, packet processing, forwarding, telemetry, programmable silicon, NoC, NIC, and DPU architectures.
- Experience with RTL generation, hardware architecture exploration, PPA optimization, simulation, formal verification, differential testing, and functional equivalence.
- Experience developing or deploying AI-assisted engineering methodologies and large-scale design or verification automation.
Nice to have
- Recognized technical contributions through patents or publications in hardware architecture, networking, or design automation.
- Proven track record of leading cross-disciplinary initiatives spanning hardware, software, AI, and engineering infrastructure.
Skills: ASIC architecture, RTL generation, packet processing, NoC, NIC, DPU
More semiconductor jobs: AMD jobs · SoC design jobs · California jobs
First seen in our index 0 days ago, well below the 82-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
486
|
Median days since first seen
82 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (486 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 486 |
| Open roles in the wider Digital Design & Verification family | 266 | 3520 · 120 employers |
| Median days since first seen | 69 d | 82 d (+13 d vs this employer) |
| Median salary (USD postings) | n/a | $230k |
Skills observed across this category: ASIC architecture, RTL generation, packet processing, NoC, NIC, DPU
Who's hiring in this category
- Qualcomm · 79 open roles · median 92 d
- NVIDIA · 67 open roles · median 84 d
- AMD (this employer) · 39 open roles · median 71 d
- Arm Holdings · 29 open roles · median 14 d
- Apple · 28 open roles · median 15 d
- Micron Technology · 20 open roles · median 114 d
How we counted: 486 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.