Engineer-Staff - Austin, Texas, United States of America, United States
$140,000 - $210,000 USD yearly
Originally posted 9 September 2026 by the employer.
Focus on IP (block/SoC) development.
About the role
This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development.
What you'll do
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development.
- Create architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate with functional teams to develop and execute an implementation strategy that meets system requirements.
- Evaluate aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification.
- Utilize tools/applications (e.g., RTL to GDS Flow, Virtuoso) for architecture and design of complex blocks/SoC or IC Packages.
- Write and review detailed technical documentation for complex EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 6 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
- 1 year of work experience in a role requiring interaction with senior leadership.
Skills: ASIC design, IP development, architectures, circuit specifications, logic designs, system-level requirements
This role has been open 35 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 72 | 470 |
| Open roles in the wider Digital Design & Verification family | 377 | 3191 · 115 employers |
| Median days open | 86 d | 79 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: ASIC design, IP development, architectures, circuit specifications, logic designs, system-level requirements
Who's hiring in this category
- Qualcomm (this employer) · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.