Engineer/ Sr Memory Layout Engineer-DPG-LPDDR - Hyderabad - Phoenix Aquila, India
Originally posted 22 July 2026 by the employer.
About the role
This role is for a Senior Memory Layout Engineer focusing on memory and storage solutions, specifically with expertise in DRAM/LPDDR memory architecture.
What you'll do
- Create Bit cell layouts and perform pitch matching.
- Develop Row decoder (XDEC) and column decoder (YDEC) layouts.
- Implement custom layouts using Cadence Virtuoso.
- Debug and ensure closure of Calibre DRC/LVS.
- Apply device physics expertise for high-quality layout implementation, including transistor matching, well and substrate engineering, parasitic optimization, and EM/ESD reliability.
- Plan, execute, and deliver layout blocks independently.
What you'll need
- 2+ years of experience in memory and full-custom layout development.
- Understanding of memory array hierarchy and decode path.
- Proficiency with Cadence Virtuoso for custom layout implementation.
- Solid experience with Calibre DRC/LVS, including debug and closure.
- Strong understanding of DRAM/LPDDR memory architecture, array organization, and peripheral integration.
- B. Tech/B. E in Electronics, Electronics & Communications, or VLSI Engineering.
Skills: Bit cell layout creation, Row decoder (XDEC), column decoder (YDEC), custom layout implementation, Calibre DRC/LVS, DRAM/LPDDR memory architecture
This role has been open 99 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: Bit cell layout creation, Row decoder (XDEC), column decoder (YDEC), custom layout implementation, Calibre DRC/LVS, DRAM/LPDDR memory architecture
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.