Engineer II - Physical Design
Originally posted 29 October 2026 by the employer.
About the role
The Engineer II - Physical Design supports semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, documentation, and tapeout-readiness activities.
What you'll do
- Develop and maintain defined ASIC or SoC physical-design blocks, constraints, scripts, flows, and design data.
- Translate approved architecture and RTL requirements into synthesis, floorplan, placement, clock, routing, timing, power, and verification objectives.
- Execute implementation, regression, extraction, timing, power, physical-verification, and applicable signoff checks.
- Troubleshoot flow, constraint, timing, congestion, power, signal-integrity, physical-verification, and integration issues.
- Coordinate assigned deliverables across architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams.
- Maintain design configuration, scripts, run records, waiver evidence, release data, traceability, and technical documentation.
What you'll need
- Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.
- 2.5–5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, physical verification, EDA flows, or closely related equivalent experience.
- Experience with timing and power analysis, debugging, and root-cause analysis.
- Experience working with complex architecture, RTL, constraints, libraries, layout, timing, power, physical-verification, reliability, and manufacturing information.
Nice to have
- Experience with EDA tools, scripting, automation, design constraints, low-power implementation, variation analysis, design-for-test, advanced process nodes, or tapeout flows.
- Experience resolving timing, congestion, power, signal-integrity, physical-verification, integration, reliability, or manufacturability issues.
- Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.
Skills: place and route, synthesis, timing closure, physical verification, ASIC, clock-tree synthesis
More semiconductor jobs: Microchip Technology jobs · Physical design jobs
This role has been open 0 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
693
|
Median days open
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (693 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 693 |
| Open roles in the wider Physical Implementation family | 30 | 1545 · 112 employers |
| Median days open | 66 d | 59 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: place and route, synthesis, timing closure, physical verification, ASIC, clock-tree synthesis
Who's hiring in this category
- Qualcomm · 114 open roles · median 51 d
- AMD · 63 open roles · median 33 d
- Synopsys · 39 open roles · median 43 d
- Intel Corporation · 38 open roles · median 21 d
- Broadcom · 37 open roles · median 99 d
- NVIDIA · 36 open roles · median 69 d
How we counted: 693 open Physical Design (Physical Design) roles from 81 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.