Engineer II - Digital ASIC Design - CA - San Jose - Fortune Dr (Micrel R&D), United States
$70,304 - $143,000 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
This role involves the implementation of complex digital IP blocks from concept to delivery, focusing on Power, Performance, and Area optimizations.
What you'll do
- Implement RTL (System Verilog) of complex digital IP blocks.
- Drive Power, Performance, and Area trade-offs and optimizations.
- Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
- Lead Lint, CDC, RDC, and formal verification efforts.
- Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
- Cooperate with teams to verify and validate module and system functions.
What you'll need
- 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
- BS degree in Electrical Engineering.
- Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
- Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
- Proficient in lab equipment (e.g., oscilloscope, logic analyzer).
Nice to have
- Familiarity with PHY or Serdes protocols.
- Knowledge of IEEE 802.3.
- Post-silicon validation or bring-up experience.
- Skillful in scripts to aid efficiency.
Skills: RTL, System Verilog, ASIC, EDA flow, PHY or Serdes protocols
This role has been open 19 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1017
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1017 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1017 |
| Open roles in the wider Digital Design & Verification family | 68 | 3171 · 114 employers |
| Median days open | 68 d | 61 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL, System Verilog, ASIC, EDA flow, PHY or Serdes protocols
Who's hiring in this category
- Qualcomm · 138 open roles · median 61 d
- Synopsys · 86 open roles · median 25 d
- AMD · 75 open roles · median 32 d
- Analog Devices · 50 open roles · median 42 d
- NXP Semiconductors · 48 open roles · median 79 d
- NVIDIA · 45 open roles · median 65 d
How we counted: 1017 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.