Emulation Verification Engineer - TX, Austin_Research Park, United States
Originally posted 10 September 2026 by the employer.
Join the team driving AMD Core's Shift-Left strategies.
About the role
What you'll do
- Interact with stakeholders (firmware/BIOS, RTL designers, DV, system architects) to plan, create, execute, and debug core on emulators.
- Define and implement test plans including stimulus, checking, and functional coverage plans.
- Develop test benches and test bench components in C++.
- Write monitors and checkers to support end-to-end core emulation infrastructure.
- Debug regression fails and fix verification issues or work with designers to fix design bugs.
- Create hardware emulation build to verify IP functional performance.
What you'll need
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
- Experience with Verilog, System Verilog, C, and C++.
- Experience debugging failures using waveform viewers, log files, and microcode trace dumps.
- Strong background in the C++ language, preferably on Linux.
- Proficient in debugging firmware and RTL code using simulation tools.
- Proficient in using UVM testbenches and working in Linux and Windows environments.
Nice to have
- Experience with FPGA and/or emulation platforms (ZeBu, HAPs, Veloce).
- Automating workflows in a distributed compute environment.
- Knowledge of UEFI, core-boot, Linux, Windows Operating Systems.
- Knowledge of x86 and/or ARM SoC Architecture.
- Coding in x86 Assembly language.
- Scripting language experience: Perl, Python, Makefile, shell.
Skills: emulation, SystemVerilog, C++, test plans, debug
This role has been open 34 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 97 | 1192 |
| Open roles in the wider Digital Design & Verification family | 255 | 3191 · 115 employers |
| Median days open | 50 d | 65 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: emulation, SystemVerilog, C++, test plans, debug
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD (this employer) · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.