Emulation Front-End Infrastructure Engineer - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 10 August 2026 by the employer.
Our Emulation Infrastructure team builds scalable hardware development platforms and compilation flows that enable pre-silicon validation of NVIDIA’s most complex designs.
About the role
This role involves owning and evolving front-end compilation, synthesis, and flow infrastructure for NVIDIA hardware emulation platforms. The team focuses on building scalable hardware development platforms and compilation flows for pre-silicon validation.
What you'll do
- Own and evolve front-end compilation, synthesis, and flow infrastructure for hardware emulation platforms.
- Develop, maintain, and automate robust compilation and synthesis flows using scripting and EDA tools.
- Run, analyze, and debug compilation and synthesis regressions; partner with logic designers to maintain RTL design stability.
- Evaluate, deploy, and support EDA tools and methodologies for front-end implementation and emulation compilation.
- Diagnose complex compilation, elaboration, synthesis, and implementation issues, collaborating with internal design teams and EDA vendors.
- Improve flow performance, reliability, scalability, usability, and observability across a large-scale hardware development environment.
What you'll need
- BS degree in Electrical Engineering, Computer Engineering, or a related field with 5+ years of relevant experience; or an MS degree in a related field with 3+ years of relevant experience.
- Experience with RTL compilation, synthesis, front-end design implementation, and flow automation.
- Proficiency in Verilog and SystemVerilog, including ability to read, debug, and modify RTL for emulation needs.
- Strong understanding of RTL elaboration, synthesis, logic optimization, and front-end design methodologies.
- Hands-on experience with front-end synthesis and compilation EDA tools, including Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.
- Automation and scripting skills in Python, Perl, Tcl, shell scripting, and Makefile-based flows.
- Experience running high volumes of jobs on distributed compute farms using workload schedulers such as LSF or Slurm, and using revision-control systems such as Perforce or Git.
Nice to have
- Experience with hardware-emulation compilation flows and runtime bring-up or debugging.
- Deep expertise with Synopsys Design Compiler, ZeBu Compiler, and Cadence HDL-ICE.
- Experience building scalable regression, reporting, monitoring, and flow-debug infrastructure.
- Experience building AI/LLM agents or automation that can classify tool logs, diagnose failures, and drive automated recovery.
- Experience partnering directly with EDA vendors to resolve complex tool, methodology, or performance issues.
Skills: hardware emulation platforms, compilation flows, synthesis, EDA tools, Verilog, SystemVerilog, Synopsys Design Compiler, ZeBu Compiler
This role has been open 67 days — below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
675
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (675 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 675 |
| Open roles in the wider Physical Implementation family | 75 | 1442 · 110 employers |
| Median days open | 69 d | 73 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: hardware emulation platforms, compilation flows, synthesis, EDA tools, Verilog, SystemVerilog
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys · 63 open roles · median 38 d
- Micron Technology · 44 open roles · median 46 d
- Qualcomm · 36 open roles · median 74 d
- GlobalFoundries · 33 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 71 d
How we counted: 675 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.