Emulation Engineer - Mountain View, CA, United States
$120,000 - $600,000 USD yearly
Originally posted 23 May 2026 by the employer.
About the role
MatX is seeking an Emulation Engineer to build the infrastructure, flows, and debug methodology behind advanced connectivity SoCs. The position creates reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation.
What you'll do
- Define and execute emulation strategy and test plans for complex connectivity SoCs. - Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, ZeBu, or Veloce. - Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests. - Drive emulation speed-ups and resource utilization across compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management. - Build automation for regression triage, debug, model usability, and LLM-based tooling for log analysis and workflow generation.
What you'll need
- Hands-on experience with SoC emulation or system-level validation. - Experience with at least one commercial emulation platform, such as Palladium. - Working Verilog/SystemVerilog and waveform-debug skills to develop custom transactors or agents. - Software and automation skills in Python plus one or more of C, C++, Rust, Tcl, or shell. - Demonstrated background building verification or emulation tools and infrastructure. - System-level debug skills spanning RTL, firmware, and software.
Nice to have
- UVM or hybrid SoC testbench development experience. - Experience integrating cycle-accurate, software, or reference models into emulation/DV flows. - Experience with Rust in verification or emulation flows. - Experience with Bazel or large-scale build/regression systems. - Experience with reusable stimulus across simulation, emulation, and post-silicon. - Domain experience in connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics. - Firmware or driver bring-up experience on emulation platforms.
Skills: emulation, palladium, zebu, speedbridge, hw/sw co-emulation, pcie
This role has been open 153 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MatX | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1254 |
| Open roles in the wider Digital Design & Verification family | 30 | 3328 · 115 employers |
| Median days open | 64 d | 64 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: emulation, palladium, zebu, speedbridge, hw/sw co-emulation, pcie
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.