Emulation Engineer / Emulation Platform Engineer -Senior - Austin, Texas, United States of America, United States
$121,800 - $182,600 USD yearly
Originally posted 1 October 2026 by the employer.
About the role
This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development.
What you'll do
- Apply ASIC knowledge and experience to define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
- Create architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate across teams to develop and execute an implementation strategy that meets system requirements.
- Evaluate all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or custom circuit design/layout flow.
- Utilize tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
- Write detailed technical documentation for EDA/IP/ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 3 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
Skills: emulation, ASIC verification, validation, IP development, system simulations, RTL to GDS Flow
This role has been open 7 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 106 | 1206 |
| Open roles in the wider Digital Design & Verification family | 389 | 3183 · 114 employers |
| Median days open | 43 d | 63 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: emulation, ASIC verification, validation, IP development, system simulations, RTL to GDS Flow
Who's hiring in this category
- Qualcomm (this employer) · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.