Electrical Packaging Design Engineer - CA, San Jose, United States
Originally posted 3 August 2026 by the employer.
Work across chip, technology, and systems teams to define cost-effective and high-performance solutions.
About the role
The Electrical Packaging Design Engineer will work across chip, technology, and systems teams to define cost-effective and high-performance solutions for multiple package families for FPGA devices.
What you'll do
- Use Cadence tools for design, modeling, and simulations, ensuring timely closure of designs. - Define package/module design requirements using analytical and simulation tools. - Conduct routing, stack-up, and component placement studies, and complete package design activities. - Collaborate with PCB Layout Engineers and chip teams to optimize package ballmap and die size. - Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures. - Perform Power Integrity analysis for core and IO, generating power delivery network requirements.
What you'll need
- Ability to understand electrical requirements and translate them to package technology requirements. - Bachelor’s or Master's degree in Engineering. - Good understanding of various Organic/PCB technologies. - Current working knowledge of Cadence package design tools. - Working knowledge of 2D/3D package design and modeling tools. - Knowledge of SerDes design and package/PCB layout constraints.
Nice to have
- Package/PCB layout experience. - Experience in high power, Gbs IO products. - Knowledge of SKILL. - Knowledge on DoE, DFM/DFR. - Ability to mentor junior package designers.
Skills: package design, Cadence tools, routing, stack-up, power integrity analysis
This role has been open 75 days — well above the 60-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
205
|
Median days open
60 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (205 roles · 42 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 205 |
| Open roles in the wider Process, Fab & Equipment family | 47 | 9897 · 109 employers |
| Median days open | 41 d | 60 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: package design, Cadence tools, routing, stack-up, power integrity analysis
Who's hiring in this category
- Renesas Electronics · 27 open roles · median 33 d
- Infineon Technologies · 24 open roles · median 48 d
- Micron Technology · 23 open roles · median 131 d
- onsemi · 13 open roles · median 26 d
- Monolithic Power Systems · 11 open roles · median 212 d
- Intel Corporation · 9 open roles · median 103 d
How we counted: 205 open Packaging Engineering (Packaging) roles from 42 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.