EDA AI/ML Layout Engineering Intern - US-CA-Calabasas, United States
$40 - $54 USD yearly
Originally posted 29 September 2026 by the employer.
This role focuses on developing AI/ML solutions for RFIC and analog IC design.
About the role
This internship involves contributing to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration for RFIC and analog IC design.
What you'll do
- Develop AI and ML solutions for RFIC and analog layout automation.
- Research and prototype machine learning techniques for layout synthesis and design optimization.
- Assist in the development of parameterized cells (PCells) and layout generation workflows.
- Contribute to surrogate modeling and design space exploration frameworks.
- Build data generation, training, and evaluation pipelines for AI-driven EDA workflows.
- Develop software components in Python and potentially C++.
What you'll need
- Currently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field.
- Strong programming skills in Python.
- Familiarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn.
- Solid understanding of data structures, algorithms, and object-oriented programming.
- Interest in AI/ML applied to engineering design automation.
Nice to have
- Coursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation.
- Familiarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation.
- Exposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques.
- Experience with C++, Rust, or performance-oriented software development.
- Exposure to software development on Windows or Linux platforms.
- Familiarity with Git and modern software development practices.
Skills: AI/ML, EDA technologies, layout automation, PCell development, RFIC
This role has been open 9 days — well below the 31-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · AI EDA Design
|
Open roles in category
61
|
Median days open
31 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (61 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 61 |
| Open roles in the wider Physical Implementation family | 37 | 1485 · 107 employers |
| Median days open | 9 d | 31 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: AI/ML, EDA technologies, layout automation, PCell development, RFIC
Who's hiring in this category
- NXP Semiconductors · 12 open roles · median 58 d
- Keysight Technologies (this employer) · 7 open roles · median 10 d
- NVIDIA · 7 open roles · median 30 d
- Cadence Design Systems · 6 open roles · median 47 d
- Altera · 3 open roles · median 2 d
- Qualcomm · 3 open roles · median 47 d
How we counted: 61 open EDA/CAD Engineering (AI EDA Design) roles from 24 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.