DV - Principal Digital Verification Engineer - Vancouver, BC OR Bay Area, CA, United States
Originally posted 27 April 2026 by the employer.
About the role
Eliyan is seeking a Principal Digital Verification Engineer to provide technical verification leadership and own end-to-end verification for connectivity IPs and chiplets. The role involves developing testbenches and unit/chip level test cases for PHYs, controllers, and microcontroller subsystems.
What you'll do
- Develop and execute verification plans for connectivity IPs and chiplets. - Create and maintain SystemVerilog/UVM-based verification environments and test cases for block and chip level. - Drive verification methodologies including constrained-based random verification and coverage-driven verification. - Create, improve, and maintain DPI-based FW simulation environments and gate-level simulation environments for functional and power simulations. - Create microcontroller subsystem testbenches, maintain regression environments for CI/CD pipelines, and integrate 3rd party VIPs. - Collaborate with design engineers on micro-architecture, test-plan, and coverage reviews through RTL freeze.
What you'll need
- BS in Electrical Engineering or related fields with 15+ years of experience. - Strong expertise in UVM, test environments, and assertion coding with SystemVerilog. - Strong expertise on coverage-driven verification and proficiency in 3rd party tools for regression management and coverage analysis. - Experience verifying 3rd party mixed signal IPs and integrating VIPs. - Experience working on connectivity interfaces and protocols. - Strong understanding of microcontroller architecture and peripherals, along with hands-on experience in scripting languages.
Nice to have
- Knowledge of IO interface.
Skills: SystemVerilog/UVM, verification plans, chiplets, coverage driven verification, mixed signal IPs
This role has been open 119 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Eliyan | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1233 |
| Open roles in the wider Digital Design & Verification family | 11 | 3298 · 115 employers |
| Median days open | 119 d | 64 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog/UVM, verification plans, chiplets, coverage driven verification, mixed signal IPs
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.