DV Intern - San Jose, United States
Originally posted 7 February 2026 by the employer.
Verify custom IPs including systolic arrays, DMA engines, and NoCs.
About the role
As a Design Verification intern, you will ensure custom IPs—including systolic arrays, DMA engines, and NoCs—are robust, high-performance, and silicon-ready. You will collaborate with architects, RTL designers, and software, firmware, and emulation teams to validate correctness and performance across the hardware-software stack.
What you'll do
- Verify custom IPs including systolic arrays, DMA engines, and NoCs. - Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. - Develop verification environments and write test benches. - Tackle complex verification challenges across high-speed digital logic and ASIC or SoC architectures.
What you'll need
- Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field. - Familiarity with high-speed digital logic. - Exposure to ASIC or SoC design concepts. - Familiarity with SystemVerilog, UVM, or Python. - Familiarity with verification work and writing test benches. - Familiarity with physical design flows and tooling.
Skills: Design Verification intern, custom IPs, test benches, SystemVerilog, UVM, formal verification
This role has been open 219 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1233 |
| Open roles in the wider Digital Design & Verification family | 13 | 3299 · 116 employers |
| Median days open | 189 d | 64 d (+125 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Design Verification intern, custom IPs, test benches, SystemVerilog, UVM, formal verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.