DV Formal Verification - Mountain View, CA, United States
$200,000 - $320,000 USD yearly
Originally posted 2 June 2026 by the employer.
Own block- and SOC-level formal verification for AI accelerator silicon.
About the role
Own block- and SOC-level formal verification, debug, and proof convergence for our AI accelerator silicon. This role supports DensityAI's AI accelerator program.
What you'll do
- Own block- and SOC-level formal verification, debug, and and proof convergence for AI accelerator silicon
What you'll need
- Exceptional abilities in formal verification: property authoring (SVA / PSL), proof strategies, and tool-flow ownership
- Master's + 8 years of experience in block- and full-chip formal verification on complex SOCs
- Demonstrated ability to debug proof failures and drive convergence in collaboration with RTL designers and architects
- Hands-on experience with industry-standard formal tools (Synopsys VC Formal, Cadence Jasper, or equivalent)
Nice to have
- Security verification
- Processor verification
- Equivalence checking
- AMS / IP-flow exposure
Skills: formal verification, block-level, SOC-level, property authoring, SVA, proof convergence
This role has been open 34 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1192 |
| Open roles in the wider Digital Design & Verification family | 5 | 3191 · 115 employers |
| Median days open | 34 d | 65 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: formal verification, block-level, SOC-level, property authoring, SVA, proof convergence
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.