DSP - FEC Design Engineer
$150,000 - $250,000 USD yearly
This DSP - FEC Design Engineer role involves building optical transceivers for optical modems.
Originally posted 16 March 2026 by the employer.
About the role
This role is for a DSP - FEC Design Engineer, focusing on developing high-performance forward error correction (FEC) algorithms for high-speed communication systems. This work supports the development of optical transceivers for optical modems.
What you'll do
- Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems.
- Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations.
- Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures.
- Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments.
- Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity.
- Develop floating-point and fixed-point simulation models for algorithm verification.
- Implement bit-accurate and cycle-accurate models supporting ASIC implementation.
- Collaborate with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation.
- Document algorithm design and simulation results.
What you'll need
- Strong theoretical background in coding theory, digital communications, and error correction techniques.
- Experience developing high-performance forward error correction (FEC) algorithms for high-speed communication systems.
- Master's or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field.
- Experience with FEC schemes for communication systems, particularly soft-decision FEC.
- Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques.
- Experience evaluating coding gain, BER performance, and decoder complexity.
- Programming experience in C/C++, Python, MATLAB, or similar languages.
- Experience in modeling communication systems.
- Familiarity with DSP algorithms for communication systems.
- Experience with version control systems, specifically GitHub.
Nice to have
- Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus.
Skills: DSP, FEC algorithms, optical communication, LDPC, MATLAB, Verilog
More semiconductor jobs: RTL design jobs · Canada jobs
First seen in our index 218 days ago, well above the 78-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
|
Open roles in category
35
|
Median days since first seen
78 d
|
Category median salary (all employers)
n/a
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (35 roles · 19 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 35 |
| Open roles in the wider Digital Design & Verification family | 6 | 3606 · 122 employers |
| Median days since first seen | 22 d | 78 d (+56 d vs this employer) |
| Median salary (USD postings) | n/a | n/a |
Skills observed across this category: DSP, FEC algorithms, optical communication, LDPC, MATLAB, Verilog
Who's hiring in this category
- Infineon Technologies · 6 open roles · median 68 d
- Celero (this employer) · 4 open roles · median 22 d
- Keysight Technologies · 3 open roles · median 123 d
- Altera · 2 open roles · median 54 d
- Lattice Semiconductor · 2 open roles · median 7 d
- Marvell Technology · 2 open roles · median 174 d
How we counted: 35 open Digital/RTL Design (Mixed Signal DSP) roles from 19 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.