Work on AI accelerator chips that integrate high-current power delivery and PCIe Gen6 interconnect.
Originally posted 27 July 2026 by the employer.
About the role
What you'll do
- Develop and execute test strategies for DRAM devices and their interconnects, covering functional, timing, signal integrity, and reliability failure modes.
- Diagnose complex DRAM issues across logical, architectural, and physical domains, including cell behavior, addressing, timing margins, and interface interactions.
- Build, modify, and maintain simulation models to study DRAM behavior, interfaces, and test scenarios at multiple abstraction levels.
- Use simulation tools to explore corner cases, stress conditions, and failure mechanisms prior to and alongside silicon testing.
- Analyze DRAM behavior with a deep understanding of circuit operation, including variability, noise, leakage, and process effects.
- Apply statistical methods to large test datasets to identify trends, characterize distributions, isolate root causes, and support yield and reliability conclusions.
What you'll need
- BS or MS in Electronics and Electrical Engineering or related field.
- Strong background in DRAM architecture, operation, and interfaces.
- Solid understanding of DRAM failure modes, and associated test and characterisation methods.
- Solid understanding of advanced CMOS electronic circuit behavior and its impact on memory operation.
- Experience applying statistics to hardware test and characterization problems.
- Strong mathematical skills applied to modeling, analysis, and problem solving in test development.
- Ability to reason rigorously across abstraction levels, from physical circuits to logical test algorithms.
Nice to have
- Experience with memory test, silicon bring-up, and failure analysis.
- Exposure to SPICE or equivalent circuit-level simulation.
- Experience analyzing high-volume test data and yield trends.
- Familiarity with manufacturing or system-level memory test environments.
Skills: DRAM Product Engineer, DRAM architecture, DRAM failure modes, simulation models, CMOS electronic circuit
This role has been open 101 days — well above the 72-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
302
|
Median days open
72 d
|
Category median salary (all employers)
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Fractile | All employers we track in this specialty (302 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 302 |
| Median days open | 62 d | 72 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM Product Engineer, DRAM architecture, DRAM failure modes, simulation models, CMOS electronic circuit
Who's hiring in this category
- Micron Technology · 154 open roles · median 82 d
- Synopsys · 30 open roles · median 77 d
- Qualcomm · 18 open roles · median 106 d
- Broadcom · 16 open roles · median 78 d
- SanDisk · 15 open roles · median 7 d
- NVIDIA · 8 open roles · median 59 d
How we counted: 302 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.