DRAM Power Engineer - Boise, ID - Main Site, United States
Originally posted 4 August 2026 by the employer.
This role focuses on AI enabled memory products.
About the role
This role is for a DRAM Power Engineer responsible for analyzing power behavior, developing models and methodologies, and influencing architectural decisions.
What you'll do
- Perform AI assisted DRAM power analysis, including IDD characterization, workload-based modeling, and power breakdown analysis.
- Develop and maintain power models, methodologies, and tools to evaluate DRAM architectures and power-performance tradeoffs.
- Translate system and customer power requirements into recommendations that drive architectural and product decisions.
- Define and support DRAM power targets throughout product development.
- Partner with Design, Product Engineering, and System Architecture teams to identify and implement power improvements.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field and 3+ years of relevant industry experience, or Master's degree/PhD in a related field.
- Experience in at least two of the following areas: DRAM architecture, memory subsystems, semiconductor fundamentals, power analysis, modeling, simulation, architecture evaluation, or technical data analysis.
- Strong problem-solving skills with the ability to analyze complex technical challenges and develop solutions.
- Ability to communicate technical concepts and collaborate effectively across engineering teams.
Nice to have
- Experience with DRAM power analysis, IDD metrics, power characterization, or memory system power optimization.
- Knowledge of workload-based power modeling, memory controller behavior, and system-level power analysis.
- Experience developing power analysis tools, automation frameworks, or architectural evaluation methodologies.
- Understanding of DRAM design tradeoffs involving power, performance, area, and reliability.
- Experience conducting competitive benchmarking and influencing technical or product decisions through data-driven insights.
Skills: DRAM power analysis, IDD characterization, workload-based modeling, power breakdown analysis, DRAM architecture
This role has been open 61 days — below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM power analysis, IDD characterization, workload-based modeling, power breakdown analysis, DRAM architecture
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.