Distinguished Engineer, Switch Architect - Bangalore, India
Originally posted 28 August 2026 by the employer.
About the role
This role defines the architecture for Marvell’s future-forward switch ASICs designed for hyperscale cloud environments, massive east-west traffic, and AI workloads. This involves shaping product definition, behavioral modeling, device performance modeling, and architectural validation.
What you'll do
- Define architecture for AI networking switch ASICs designed for hyperscale cloud and ML/AI-driven workloads.
- Anticipate and analyze emerging technology trends, influencing long-term roadmap and architectural direction.
- Contribute to the development of industry standards including Ultra Ethernet and Ultra Accelerator Link (UAL).
- Create and maintain architectural and performance models to evaluate trade-offs in latency, power, bandwidth, and scalability.
- Collaborate with silicon, software, systems, and product teams to drive holistic architectural alignment.
- Provide architectural mentorship and leadership to engineering teams across the organization.
What you'll need
- BS with 15+ years, MS with 10+ years, or PhD with 8+ years in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Extensive experience defining and architecting large-scale ASICs and complex networking semiconductor architectures.
- Deep architectural understanding of high-speed interconnects and Ethernet protocols.
- Deep architectural understanding of traffic management architectures and packet processing.
- Deep architectural understanding of scaling networks in AI training and inference fabrics.
- Hands-on experience with performance modeling, simulation, and architectural trade-off analysis.
- Proficiency in C/C++, Python, and modeling environments.
Nice to have
- Experience contributing to or leading standards development.
Skills: switch ASICs, AI networking, hyperscale cloud, performance modeling, Ethernet protocols, traffic management
This role has been open 31 days — well below the 73-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
431
|
Median days open
73 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (431 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 431 |
| Open roles in the wider Digital Design & Verification family | 28 | 3077 · 114 employers |
| Median days open | 26 d | 73 d (−47 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: switch ASICs, AI networking, hyperscale cloud, performance modeling, Ethernet protocols, traffic management
Who's hiring in this category
- Qualcomm · 72 open roles · median 78 d
- NVIDIA · 56 open roles · median 52 d
- AMD · 35 open roles · median 80 d
- Arm Holdings · 27 open roles · median 95 d
- NXP Semiconductors · 19 open roles · median 97 d
- Renesas Electronics · 16 open roles · median 120 d
How we counted: 431 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.