Director, Test Solutions Engineering Manager (West Coast Region)
Originally posted 1 August 2026 by the employer — open 40 days.
About the role
This role involves establishing, staffing, and leading a new Test Solutions Engineering (TSE) team in the Santa Clara US region, owning ATE based production test development for Marvell's custom data center silicon.
What you'll do
- Build and scale the West Coast Test Solutions Engineering team, including hiring, onboarding, and developing engineering talent.
- Lead end-to-end New Product Introduction (NPI) for assigned programs, from design start through production ramp.
- Own test strategy definition, architecture, and overall solution readiness for high-volume manufacturing.
- Drive silicon bring-up, debug, and characterization to validate production test coverage and performance.
- Serve as the primary technical and managerial interface to customers for test strategy alignment and issue resolution.
- Implement continuous improvement initiatives across test processes, yield, and test cost.
What you'll need
- Bachelor’s degree or higher in electrical engineering, Computer Engineering, Computer Science, or related field.
- 10-15 years of experience in Custom processor / ASIC Product Engineering, Test Engineering, DFT, or Technology Characterization.
- Demonstrated success managing or leading engineering teams.
- Strong understanding of Product Engineering and Test Development, Design-for-Test (DFT), semiconductor devices and process technology, and Quality and reliability practices.
- Proven ability to lead complex technical programs and drive cross-functional alignment.
Nice to have
- Master’s or PhD in EE/CS.
- Experience hiring and building new teams or leading organizational expansion.
- Experience supporting hyperscale or large enterprise customers.
- Experience working with global or distributed engineering teams.
This role has been open 40 days — well above the 22-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
302
|
Median days open
22 d
|
Median salary
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (302 roles · 60 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 302 |
| Open roles in the wider Silicon Validation & Test family | 54 | 1959 · 109 employers |
| Median days open | 38 d | 22 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Infineon Technologies · 30 open roles · median 19 d
- Renesas Electronics · 29 open roles · median 23 d
- Qualcomm · 19 open roles · median 21 d
- AMD · 18 open roles · median 21 d
- Micron Technology · 17 open roles · median 17 d
- NVIDIA · 16 open roles · median 15 d
How we counted: 302 open Silicon Test Engineering (DFT Test) roles from 60 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.