Director, System in Package Architecture - San Jose, CA, United States
$240,000 - $300,000 USD yearly
Originally posted 6 July 2026 by the employer.
Focus on System in Package (SiP) architecture and SOC integration with High Bandwidth Memory (HBM) in 2.5D and 3D packaging environments.
About the role
The Director, System in Package Architecture leads the end-to-end development of advanced packaging system architectures to maximize System in Package (SiP) performance, focusing specifically on High Bandwidth Memory (HBM).
What you'll do
- Lead the end-to-end development of advanced packaging system architectures to maximize System in Package (SiP) performance, with a specific focus on High Bandwidth Memory (HBM). - Drive mechanical and electrical test vehicle design and development when necessary. - Spearhead research and development of novel technologies to enhance SiP performance, driving the roadmap for SOC and HBM integration in 2.5D and 3D packaging environments. - Lead strategic collaborations with internal teams and external partners to ensure seamless technology development and time-to-market.
What you'll need
- BS in Electrical Engineering or equivalent combination of education and progressive industry experience. - 7+ years of specialized experience in advanced packaging architecture definition, strategy, and development. - Demonstrated success in driving cross-functional alignment across engineering, product, and operations teams to deliver complex solutions. - Proven track record of leading, mentoring, and scaling high-performing engineering teams, with experience managing managers or team leads preferred. - Exceptional verbal and written communication skills, with the ability to articulate technical strategies.
Nice to have
- Master’s degree or PhD in Electrical Engineering, Materials Science, or related field. - 10+ years of experience in advanced packaging architecture, specifically with 2.5D and 3D packaging technologies. - Expert working knowledge of 2.5D/3D packaging technologies and large body substrate technologies. - Strong proficiency in Signal Integrity (SI) and Power Integrity (PI) analysis and optimization. - Direct experience in High Bandwidth Memory (HBM) architecture and integration.
Skills: advanced packaging, System in Package, HBM, 2.5D, 3D packaging
This role has been open 106 days — well below the 120-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
120 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 39 |
| Median days open | 157 d | 120 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: advanced packaging, System in Package, HBM, 2.5D, 3D packaging
Who's hiring in this category
- Qualcomm · 5 open roles · median 113 d
- Intel Corporation · 4 open roles · median 37 d
- Marvell Technology · 4 open roles · median 104 d
- Micron Technology · 4 open roles · median 160 d
- NVIDIA · 4 open roles · median 72 d
- GlobalFoundries · 3 open roles · median 40 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.