Originally posted 21 August 2026 by the employer.
This role defines and executes the test strategy for analog, mixed-signal, or power management products.
About the role
This role leads a worldwide organization of test managers, architects, and engineers to define and execute the test strategy across wafer sort, final test, characterization, and qualification. The role focuses on driving standardization of methodologies, hardware architectures, and ATE platforms.
What you'll do
- Lead a worldwide organization of test managers, architects, and engineers - Define and execute the test strategy across wafer sort, final test, characterization, and qualification - Own test cost, driving test time reduction, multisite scaling, and hardware efficiency - Engage early in product planning to shift DFT, characterization, and production readiness left - Drive rapid resolution of yield excursions, test escapes, and customer returns - Lead adoption of automation, data systems, and AI-enabled engineering practices
What you'll need
- 15+ years of semiconductor test engineering experience - 8+ years leading engineering teams and managers - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline - Proven record developing ATE solutions for analog, mixed-signal, or power management products - Demonstrated success leading geographically distributed teams - Strong command of characterization, qualification, yield analysis, and production test methodology - Track record of driving test cost reduction and organizational transformation Nice to have - Experience with SPEA, ETS, V93K or Cohu platform
This role has been open 55 days — well above the 29-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
543
|
Median days open
29 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (543 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 543 |
| Open roles in the wider Silicon Validation & Test family | 118 | 2216 · 112 employers |
| Median days open | 23 d | 29 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 71 open roles · median 23 d
- Renesas Electronics (this employer) · 44 open roles · median 23 d
- Infineon Technologies · 41 open roles · median 38 d
- Qualcomm · 28 open roles · median 28 d
- Micron Technology · 27 open roles · median 36 d
- Texas Instruments · 24 open roles · median 23 d
How we counted: 543 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.