Director of Digital Design Engineering, Memory Interface IP
Originally posted 13 September 2026 by the employer.
Lead a team building memory interface IP that powers AI and high-performance compute.
About the role
This role involves leading a team of ASIC digital design and verification engineers focused on HBM, DDR, and LPDDR memory interface IP. You will lead a team building memory interface IP that powers the next wave of AI and high-performance compute.
What you'll do
- Lead a team of ASIC digital design and verification engineers working on HBM, DDR, and LPDDR memory interface IP.
- Own the technical direction and execution of RTL design and verification at both block and chip integration levels.
- Drive design reviews, architecture decisions, and quality checkpoints across the full development cycle from spec to silicon.
- Collaborate with cross-functional teams including analog design, DFT, physical design, and product management.
- Manage project timelines, resource allocation, and risk mitigation to deliver on schedule and within scope.
- Mentor and develop engineers, providing technical guidance and career growth opportunities.
What you'll need
- 15 - 20+ years of experience in ASIC digital design and verification, with hands-on work in memory interface IP such as HBM, DDR, or LPDDR.
- Proven track record leading engineering teams through full product development cycles from architecture to silicon bring-up.
- Deep expertise in RTL design, verification methodologies, and design closure for high-speed digital interfaces.
- Strong understanding of memory protocols, PHY/controller architecture, signal integrity, and timing closure challenges.
- Experience managing cross-functional collaboration with analog, physical design, and product teams.
- Demonstrated ability to communicate technical risks, tradeoffs, and project status to executive leadership and stakeholders.
Nice to have
- Experience with AI-driven design tools or a strong interest in integrating AI into design and verification flows.
This role has been open 20 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 68 | 968 |
| Open roles in the wider Digital Design & Verification family | 152 | 3109 · 114 employers |
| Median days open | 25 d | 62 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys (this employer) · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.