Director of ASIC Design Verification - San Jose, California, United States

Originally posted 19 August 2026 by the employer.

About the role

This role involves setting verification architecture and strategy across the full chip and being accountable for pre-silicon quality through tape-out, spanning block through full-chip and gate-level benches, performance verification, coverage closure, and emulation and FPGA prototyping.

What you'll do

• Own pre-silicon functional and performance verification for SambaNova ASICs, including quality, coverage closure, and on-time delivery to tape-out.
• Define verification architecture, strategy, schedules, and DV environments for complex, high-performance machine learning ASICs.
• Serve as the technical authority on verification, arbitrating testbench architecture, setting coverage and sign-off criteria, and leading debug on the hardest failures.
• Own the DV methodology end to end, including verification architecture, reuse strategy, and sign-off criteria.
• Lead, coach, and retain principal-level verification engineers, being accountable for their development and continued engagement.
• Partner with architecture, design, and software teams to settle requirements and drive DV planning.

What you'll need

• BS in EE, CS, or CE with 12+ years of industry experience in ASIC design verification.
• 5+ years managing design verification engineers, including hiring and performance management, with experience leading senior and principal-level engineers.
• Deep, current technical expertise in verification, able to own methodology, arbitrate testbench architecture, and personally lead debug on the hardest pre-silicon failures.
• Full-cycle DV from planning through tape-out and into production silicon on at least one complex ASIC or large subsystem.
• Deep hands-on foundation in SystemVerilog, SVA, Python, and industry verification methodologies such as UVM, OVM, or VMM.
• Experience through silicon bring-up, including lab functional validation and debugging first-silicon issues to root cause.
• Working knowledge of machine learning SoCs or microprocessors (CPU/GPU) and modern computer architecture.

Nice to have

• MS or PhD in EECS with 15+ years of experience in ASIC design verification.
• Multiple large-scale, high-impact chips led to silicon.
• Scaling a DV team through a step change in headcount or chip complexity.
• Owning or directing post-silicon functional validation in a lab environment.
• Deep understanding of performance verification methodology.
• High-performance interconnect protocols (PCIe, Ethernet) and memory subsystems.
• Advanced TSMC nodes and modern multi-die or chiplet verification challenges.
• Emulation and FPGA prototyping platforms.
• Managing cross-site or distributed teams.
• Fluency with Claude or other AI tools applied to verification and flow development.

Skills: ASIC design verification, SystemVerilog, UVM, coverage closure, emulation and FPGA prototyping