Director, IC Packaging Engineering – Mechanical Simulation
$227,300 - $340,900 USD yearly
Originally posted 26 June 2026 by the employer.
About the role
This position is a senior leadership role within Qualcomm's Integrated Circuits (IC) Packaging organization, leading a team of engineers responsible for delivering FEA-based mechanical simulation solutions across High Volume Manufacturing (HVM) and advanced packaging programs. The technical scope centers on mechanical FEA models (ANSYS APDL), material characterization, Warpage, Solder Joint Reliability (SJR), Board Level Reliability (BLR), and Chip-Package Interaction (CPI).
What you'll do
- Lead a mechanical simulation engineering team delivering FEA-based models and stress/mechanical analyses for IC package designs. - Oversee the development and validation of mechanical FEA models using ANSYS APDL, establishing BKM methodology for test correlation and material characterization. - Drive strategic alignment across IC package design/architecture, New Product Introduction (NPI), assembly, and Chip-Package Interaction (CPI) teams. - Guide mechanical simulation scope including Warpage, Solder Joint Reliability (SJR), package assembly process simulation, Board Level Reliability (BLR), and Chip-Package-Board interaction. - Direct simulation workflows, automation, and tooling frameworks to improve team efficiency and scalability.
What you'll need
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field with 8+ years of System/Package Design/Technology Engineering or related experience (or Master's with 7+ years, or PhD with 6+ years). - Experience leading or contributing to IC package design, technology engineering, or mechanical packaging reliability. - Technical background in mechanical simulation methods and package engineering workflows.
Nice to have
- Ph.D. in Mechanical Engineering, Materials Science, Electrical/Microelectronics Engineering, or related field. - 12 years of combined experience in Finite Element modeling and analysis for IC electronic packaging and interconnects. - 5 years of direct people management, with experience managing managers or senior technical staff. - Experience establishing simulation BKMs, methodologies, and automation frameworks such as APDL macros, OptiSLang, and scripting/automation pipelines. - Experience with material testing for strength and fracture, including designing and executing mechanical test methods. - Publications or patents in FEA predictive modeling, Warpage/SJR, and/or interfacial fracture testing.
This role has been open 118 days — well above the 51-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
1003
|
Median days open
51 d
|
Median salary
$155k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1003 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 1003 |
| Open roles in the wider Software, Firmware & Systems family | 734 | 6298 · 145 employers |
| Median days open | 52 d | 51 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $155k |
Who's hiring in this category
- Intel Corporation · 72 open roles · median 34 d
- KLA Corporation · 63 open roles · median 48 d
- Teradyne · 61 open roles · median 34 d
- NVIDIA · 53 open roles · median 72 d
- Applied Materials · 51 open roles · median 70 d
- AMD · 46 open roles · median 52 d
How we counted: 1003 open Hardware Systems Engineering (AI ML Hardware) roles from 104 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.